One Hot Decoder Verilog Implementation

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module OneHotDecoder #(
parameter integer NUM_BITS = 16
)(
input[NUM_BITS-1:0] bits,
output[$clog2(NUM_BITS)-1:0] idx
);

wire [$clog2(NUM_BITS)-1:0] stage[0:NUM_BITS];
assign stage[0] = 0;// desired default output if not bits set

genvar i;
generate
for (i = 0; i < NUM_BITS; i = i+1) begin
assign stage[i+1] = bits[i +: 1] ? i : stage[i];
end
endgenerate

assign idx = stage[NUM_BITS];

endmodule // OneHotDecoder

References

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